December 4, 2020

Nuvia Raises $240M for CPU Development, Releases New Details

We’ve been following some of the smaller CPU vendors like Nuvia and Ampere that have...

We’ve been following some of the smaller CPU vendors like Nuvia and Ampere that have emerged as potential challengers to x86 in the hyperscale server industry. This time around, Nuvia is the news — I’ll spare you the pun — for raising a massive $240M in funding as it seeks investor support to challenge companies like Intel and AMD.

Funding rounds aren’t the sort of thing we cover much at ET, but I had the opportunity to chat with John Bruno, SVP of Nuvia, and a previous SoC and chip developer with Google, Apple, AMD, and ATI. One question that’s been on my mind, since Nuvia announced its Phoenix CPU is much faster than Zen 2 while using less power, is this: Is the company betting its performance on the ARM architecture, specifically?

This isn’t just an incidental point. Talk to an x86 engineer — from either Intel or AMD — and they’ll tell you that the decode penalty x86 pays for turning CISC into RISC inside the core is tiny these days. On the ARM side of things, there’s a myth that floats around claiming that ARM chips can beat x86 because of some supposed inefficiency between CISC and RISC designs. It’s an argument that’s literally more than 25 years out of date, unless we’re talking about the performance of Intel’s Medfield versus a Cortex-A9. The Bonnell and Saltwell-core Atoms (OG 45nm and its 32nm die shrink) are the only chips that decode native x86 that aren’t old enough to vote.

According to Bruno, the idea that the CPU’s high performance requires the ARM ISA isn’t entirely true, though Nuvia’s first-generation chip is implemented using one of ARM’s custom architecture license. According to him, the core’s expected performance is the result of “micro-architecture, architecture, and implementation.”

Note: We typically use micro-architecture and architecture practically synonymously, but they aren’t synonymous. In this context, “architecture” refers to the instruction set architecture (ARMv8.x or ARMv9). “Microarchitecture,” then, is the specifics of how a semiconductor company executes an ISA within the CPU. “Implementation,” in the example above, refers to process node and foundry tech — basically, the improvements and advantages Nuvia expects its foundry partners to deliver on their side of the equation.

Nuvia’s goal is to deliver a CPU that can challenge companies like Intel and AMD — as well as Ampere, Graviton, and some of the other ARM players — across all fronts. This isn’t as banal as it sounds. We’ve seen companies adopt a variety of strategies in an effort to differentiate their products, including a number that emphasize high core counts as opposed to per-thread scaling. Nuvia’s claim, as stated in a blog post from August, is that its upcoming Phoenix core “performs up to 2X faster than the competition” when compared within a 1W – 4.5W envelope.

There are a few ways to read this. First, Nuvia is picking a data point that favors its own designs. x86 CPUs, generally speaking, don’t always run that low. AMD’s 3990X squeezes down into about 3W per-core at 3GHz. This is where Nuvia thinks it can offer still-higher efficiency.

The 3990X is itself an example of how potent these gains can be. If AMD could deliver 3GHz in 2W instead of 3W, it would knock 64W off its 280W TDP target or use the additional watt to bring clock speeds up per-core. Nuvia thinks it can hit these improvements even after considering the expected gains from CPUs like AMD’s upcoming Zen 3 architecture. AMD, if you ask (we asked) will tell you that it isn’t particularly worried.

In an article earlier this week, I argued that we’re on the cusp of the most exciting CPU market in 30+ years. Ironically, I forgot to mention Graviton, Amazon’s server CPU play, but they’re another ARM player to watch. Some readers have floated the idea that the x86 server market is simply too big, too optimized, for other companies to dent it. The list of companies that used to think this way is long, storied, and mostly dead. Of the various RISC vendors that believed their vertically-integrated semi-monopolies safe from Intel to one degree or another, the only one left standing is IBM, with a hardware business that’s a shadow of the titan it once was.

x86 has all of the powerful advantages of incumbency. It has the weight of familiarity, the robust ecosystem only a few decades of being “the standard” can bring you, and the attention of a large group of engineers from multiple companies, all of whom are dedicated to improving its performance. x86 is formidable, in ways people who mock the architecture seldom like to admit.

But formidable and “invulnerable” are not synonyms. The advent of AI and ML accelerators has at least temporarily cracked open a sclerotic market. Big things are afoot in the space, and while it’s going to be a few years before we see major changes, we’ll all be the beneficiaries of the renewed competitive focus in the CPU market long term.

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